ASIP-eFPGA Architecture for Multioperable GNSS Receivers

authored by

Thorsten Von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll

Abstract

In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.

External Organisation(s)

RWTH Aachen University

Type

Conference contribution

Pages

136-145

No. of pages

10

Publication date

2008

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Theoretical Computer Science, General Computer Science

Sustainable Development Goals

SDG 7 - Affordable and Clean Energy

Electronic version(s)

https://doi.org/10.1007/978-3-540-70550-5_15 (Access: Closed)